1. Field of the Invention
The invention relates generally to systems and methods for managing power consumption by components in an electronic device, and more particularly to systems and methods for improving power usage characteristics such as the rate of change of current (di/dt) in integrated circuits such as microprocessors.
2. Related Art
When integrated circuits such as processors are operated, they draw current from a power source. The logic components within an integrated circuit typically operate based on a clock signal, so the current drawn by the integrated circuit may suddenly increase at certain points in the clock cycle (e.g. at the rising edge of each clock cycle.) The high rate of change of the current (high di/dt) may cause electromagnetic interference (EMI) and/or noise in the power supply. Both EMI and power supply noise are undesirable.
Reducing EMI and power supply noise is becoming more and more important in designing electronic systems. This is true for a number of reasons. For instance, because it is desirable to increase the number of operations that can be performed by processors in a given amount of time, clock frequencies are increasing. The increased clock frequencies make the processors more susceptible to EMI and power supply noise. It is also desirable to design integrated circuits to use less power, so power supply voltages are decreasing. These decreased power supply voltages also make the integrated circuits more susceptible to EMI and power supply noise. Still further, because it is desirable to increase computational power, processors may include multiple processor cores, each of which contributes to di/dt and thereby creates more noise and EMI.
In some conventional multiprocessor systems, tasks are performed on the system's processor cores without consideration of di/dt. FIG. 1A illustrates a multiprocessor system in which a single clocking signal (system clock signal, CLK1) is provided to all of the system's processor cores. In some other conventional multiprocessor systems, di/dt is reduced by operating different processor cores with incrementally delayed clock signals. The switching noise and di/dt contributions associated with each processor core are distributed over a clock cycle using this method. A system of this type is illustrated in FIG. 1B. The clock signals provided to the processor cores are shown in FIG. 1C.
While the use of incrementally delayed clock signals for the different processor cores does reduce di/dt to some extent, it would be desirable to provide systems and methods for further reducing di/dt in integrated circuits generally, and in multiprocessor systems in particular.